Previously designed methods of determining which blocks of set-associative blocks in a cache memory are unavailable for replacement utilize communication between the two memory nodes to keep each node informed as to which block is being replaced. This method requires that the two nodes communicate with each other, via bus transfers, to keep the other apprised of memory block availability. By this method, neither node could exercise independent judgment on the status of memory block availability.
While the prior art provides a very adequate method of determining memory block availability, there is a need for advancement. In particular, in a high performance computer system, a major bottleneck to processing speed is bus transfers. Thus, it is imperative to minimize bus transfers to improve processing speed on a bandwidth critical bus.